This invention generally relates to semiconductor wafers having solder bump interconnects. More particularly, it relates to evaporated solder bumps. Even more particularly, it relates to an improved shadow mask for evaporating solder bumps.
Semiconductor wafer fabrication concludes with forming contacts to access circuitry on the wafer. Increasingly flip chip bonds formed of solder bumps are being used for contacts since a very large number of contacts can be provided in an area array. Evaporation or sputtering through a shadow mask made of a thin sheet of molybdenum has long been used for forming the solder bumps.
Traditionally, a high reliability solder bump connection has been achieved by providing a solder bump with a very high lead content. This has been acceptable for solder bump contacts to ceramic substrates that can tolerate the high temperature needed to melt high lead content solder. However, for connection to low temperature substrates, such as plastic substrates, a composition that provides a low melting point tin cap on a standard reflowed high-lead composition solder bump is desired, as described in commonly assigned U.S. Pat. No. 5,729,896, to Dalal et al., incorporated herein by reference. A two-mask process for forming these tin cap solder bumps is described in commonly assigned U.S. Pat. No. 5,922,496, to Dalal et al., incorporated herein by reference. However, the present inventors found that the second mask for tin cap deposition damages high melting point solder bumps formed in the first masking step. Thus, a solution is needed that improves the process to avoid damage to solder bumps formed in the first masking step.
In addition, the invention also provides a solution to a second problem. After the first shadow mask has been positioned, the wafer is subjected to a plasma etching step to remove oxide that may be covering contact pads, to reduce contact resistance between contact pads and ball limiting metallurgy that underlies the solder bump. Portions of the wafer that are covered by the molybdenum mask are protected from the plasma while contacts that are located under holes in the mask are subjected to the plasma and have oxide removed. However, uniformity of oxide removal across the wafer has been a problem, and some regions of the wafer were found to have lower contact resistance than others. Thus, a better solution for plasma etching is required to provide a way to provide more consistent low contact resistance across the wafer. A solution that both provides substantially improved contact resistance uniformity as well as avoiding damage to solder bumps if a second masking and deposition step is used, is provided by the following invention.
It is therefore an object of the present invention to provide a wafer having perimeter chips wherein additional dummy solder bumps are located adjacent each of the perimeter chips.
It is a further object of the present invention to provide a shadow mask for depositing ball limiting metallurgy and solder bumps on chips on a wafer wherein additional holes are provided in the mask adjacent all perimeter chips.
It is a further object of the present invention to improve uniformity of plasma etching of chip contacts through holes in a shadow mask by providing additional holes in the mask adjacent all perimeter chips.
It is a further object of the present invention to avoid damage to chip solder bumps on a wafer when a shadow mask is placed on the wafer for a second solder deposition by providing additional solder bumps on the wafer adjacent all perimeter chips.
It is a feature of the present invention that lanes are provided in the additional solder bumps to facilitate dicing of the wafer.
It is a feature of the present invention that a fully populated array of additional solder bumps is provided between dicing lanes at least extending to an exclusion zone along a periphery of the wafer even if the solder bumps array on product chips is not fully populated.
It is an advantage of the present invention that electric field uniformity is maintained to a radius extending beyond perimeter chips on the wafer.
It is an advantage of the present invention that contact resistance uniformity is improved and that contact resistance of perimeter chips is reduced.
It is an advantage of the present invention that damage to solder bumps on perimeter chips is reduced or avoided when a second solder deposition is provided through a second shadow mask since the additional solder bumps provide support for the second shadow mask.
These and other objects, features, and advantages of the invention are accomplished by a wafer that comprises an array of chips having contacts. The contacts comprise solder bumps. The array of chips includes perimeter chips extending along a periphery of the wafer. Additional dummy solder bumps are located adjacent most of the perimeter chips wherein the additional dummy solder bumps are for improving contact processing of the perimeter chips.
The improved contact processing includes avoiding damage during a second masking step to deposit additional solder on the solder bumps. It also includes lower contact resistance between chip metal and ball limited metallurgy as a result of superior sputter etching of contacts located along the perimeter of the chip array. Ball limited metallurgy includes metals such as chromium, copper, and gold.
A second aspect of the invention is a shadow mask, comprising an array of holes in the shadow mask corresponding to contacts on an array of chips on a wafer. The array of chips includes perimeter chips extending along a periphery of the wafer. Additional dummy holes are in the shadow mask located adjacent holes corresponding to most of the perimeter chips. The additional dummy holes are for improving contact processing of the perimeter chips.